vfpga-runner

vfpga-runner is a HOST module: it declares the full I/O superset it can wire, and a loaded .vfpga declarative spec — a "virtual FPGA bitstream" — selects which subset is ACTIVE and what render-graph runs. Swap a compiled effect into the one reconfigurable card the way a bitstream reconfigures an FPGA fabric. (The metaphor is inspired by — not a clone of — classic video-synth hardware; every VFPGA id stays generic.)

The host superset

• Video in: vin1 … vin4
• CV in: cv1 … cv4 (linear-scaled; each with a bipolar SCALE attenuverter + OFFSET + always-on scope on the card)
• Gate in: g1 … g4 (raw passthrough + a factory hysteresis edge-detector → held level / rising-edge count uniforms)
• Video out: vout1 (canonical) and vout2
• Params: a generic p1 … p8 slot bank; a loaded spec maps + labels its params onto these

The card renders the full superset of handles (inactive ports dimmed) and shows only the loaded spec's active CV inputs, gate inputs, and param knobs. Pick a VFPGA from the card's load preset… menu to hot-swap the effect.

Bundled VFPGAs

• chroma-rot — chroma-rot 2 video in · 2 video out · 2 CV · 1 gate · 5 params

  A composite-era circuit-bent VFPGA that corrupts the colour subsystem — the chroma demodulator and colour-burst phase. It separates the picture into luma + a YIQ chroma vector then mis-phases the chroma: a burst-phase offset spins the hue globally (rainbowing), a chroma-gain overdrive bleeds oversaturation, an I/Q swap mangles the colour axes, and a dot-crawl term shimmers chroma per scanline (comb-filter defeat). Because composite splits Y from C, it doubles as an S-video Y/C tool: patch a CHROMA SOURCE to IIN2 and p5 (cxfer) transplants that clip’s colours onto IIN1’s luma (clip A’s shapes in clip B’s colours) — cxfer=0 or an unpatched IIN2 leaves the original single-source bend untouched. vout2 outputs the separated luma (Y) plane. CIN1 adds a continuous hue spin onto the burst phase; CIN2 adds onto the transplant; GIN1 is a HELD gate that toggles the I/Q swap.

• databend-cvbs — databend-cvbs 1 video in · 1 video out · 1 CV · 1 gate · 4 params

  A composite-as-data circuit-bent VFPGA that databends the picture. A real 4-input bitwise LUT (the literal FPGA LUT16 truth table) mangles the picture's luma bit-planes into a bit-error field, a datapath bend byte-shifts / sample-drops / level-wraps the picture, and the two are XOR-combined (an absolute difference). p1 sweeps the LUT truth table (the XOR mask), p2 the byte-shift, p3 the sample-hold dropout density, p4 the level wrap-around. CIN1 adds onto the shift; GIN1 re-rolls the corruption seed. Every "random" bend is deterministic (frame + pixel + seed hashed) so it is reproducible.

• framestore-howl — framestore-howl 1 video in · 2 video out · 1 CV · 1 gate · 4 params

  The feedback flagship: a frame-store / howl-around circuit-bent VFPGA. A register tile holds the frame store; each frame the previous frame is read back, warped (zoomed, rotated, hue-spun, decayed) and re-mixed with the live input, then re-stored — the classic video howl-around / buffer-recirculation bend. Feedback gain past ~1 with decay near 1 gives runaway trails; the zoom drives a tunnel/spiral howl and the per-frame hue-shift a rainbow howl. CIN1 adds onto the zoom; GIN1 is a held gate that clears the store. The register ping-pong FBOs are render-local GPU state, swapped in place (no leak, no Y.Doc writes). vout1 is the composited howl; vout2 is the FRAME-STORE SEND — the warped recirculated frame (the feedback content before it remixes with the live input) — so you can scope, record, or externally process the howl loop.

• macroblock-mosh — macroblock-mosh 2 video in · 1 video out · 2 CV · 1 gate · 5 params

  An early-HD circuit-bent VFPGA that datamoshes the picture — MPEG/H.264 motion-compensated block prediction applied to the wrong reference, the classic I-frame-removal mosh. A register frame-store holds the reference; each frame the previous frame is read back, warped block-by-block by motion-vectors (the P-frame smear), macroblock-quantized (the DCT-block look), and re-mixed with the live input before being re-stored. The block motion combines a synthetic seeded storm (p2) with TRANSFERRED motion from a SECOND clip: patch a motion source to IIN2 and the bend estimates that clip’s per-block motion and carries it onto the picture (the canonical two-clip datamosh — clip B’s motion vectors on clip A). p1 sets the mosh amount (P-frame vs live), p2 the synthetic motion gain, p3 the block size, p4 the quantize, p5 the transferred-motion gain (0 + IIN2 unpatched = the original single-source mosh). CIN1/CIN2 add onto the two motion gains; GIN1 is a held gate that forces a clean I-frame (a reference reload). Every synthetic motion-vector is deterministic (frame + block + seed hashed) and the transferred motion is a deterministic normal-flow estimate, so the bend is reproducible. Both register frame-store ping-pong FBOs are render-local GPU state, swapped in place (no leak, no Y.Doc writes).

• scaler-glitch — scaler-glitch 1 video in · 1 video out · 1 CV · 1 gate · 4 params

  An early-HD circuit-bent VFPGA that corrupts the upscaler / line-doubler / deinterlacer of a cheap SD→HD set-top box. The star is a BRAM line buffer — the authentic FPGA video staple: a scaler reads a window of prior scanlines out of an on-chip line buffer and resamples them to the output raster. Bending it = addressing those rows wrong: a deinterlace error gives comb/weave zipper edges on alternating lines (field mismatch), corrupt bilinear tap weights snap to nearest-neighbour blockiness, a wrong scale ratio stretches the picture, and a line-buffer overrun re-reads a stale row as a stuck-row horizontal smear. p1 sets the deinterlace error (weave↔bob zipper), p2 the scale ratio, p3 the tap-weight corruption, p4 the stuck-row density. CIN1 adds onto the scale ratio; GIN1 flips the field parity (a fresh field mismatch). Every "random" term is deterministic (row + seed hashed) so the bend is reproducible.

• smpte-bars — SMPTE bars 0 video in · 1 video out · 1 CV · 0 gate · 2 params

  A pure pattern generator that renders SMPTE-style colour bars (the public SMPTE EG 1-1990 test-pattern layout): a top band of seven 75%-amplitude bars (grey, yellow, cyan, green, magenta, red, blue), a reverse castellation row, and a PLUGE / sub-black row. Zero video inputs, one video output — a deterministic, always-on reference source for bringing up and calibrating downstream video effects.

• sync-bender — sync-bender 1 video in · 1 video out · 1 CV · 1 gate · 4 params

  A composite-era circuit-bent VFPGA that corrupts the NTSC/PAL CVBS horizontal + vertical sync separator — the classic rolling, tearing, torn-frame and line-slip TV bend. H-phase jitter slips each scanline sideways, V-roll scrolls the picture (lost vertical lock), sync-crush shears the frame above a moving break line, and a tear-probability rips unlucky lines. Every "random" bend is deterministic (frame + pixel + seed hashed) so it is reproducible; a reseed gate (GIN1) advances the seed for a one-shot tear burst, and a CV (CIN1) adds onto the roll speed.

• tmds-sparkle — tmds-sparkle 1 video in · 1 video out · 1 CV · 1 gate · 4 params

  An early-HD circuit-bent VFPGA that corrupts the HDMI/DVI TMDS digital link — the shimmering sparkle / bit-error look of a marginal HDMI cable. A real 4-input bitwise LUT (the literal FPGA LUT16 truth table) wired over the picture's bit-planes is the per-pixel TMDS bit-flip field; that bit-error field is XOR-combined onto a datapath that adds the rest of the bent-link artifacts — a DC-balance break drifts the running disparity into horizontal banding, a character-boundary slip shears each scanline sideways, and a control-period leak bleeds saturated sync-character speckle into the active video. p1 sets the bit-error rate (the sparkle density), p2 the LUT truth table (the flip mask), p3 the disparity drift, p4 the char-slip. CIN1 adds onto the error rate; GIN1 re-rolls the error seed (a cable-wiggle burst). Every "random" error is deterministic (frame + pixel + seed hashed) so the bend is reproducible.